Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

15.5.1.1. ROM Tables & Topology Detection

Depending on the requirements of the system, CoreSight* components can be connected together in many different ways. Debuggers use the topology detection process to detect the component connections.

CoreSight* systems can have several interface types, as transmitter and receiver, requester and completer, or manager and subordinate, and each CoreSight* component specifies which interfaces are present. The debugger probes each interface to determine which other components are connected to it.

When connecting to a CoreSight* system, a debugger performs the following steps:

  1. The debugger finds the debug port (DAP SWJ-DP).
  2. The debugger ensures that the system is powered up, and that its clocks are running. The debug port provides facilities to assist with this assessment.
    1. The debugger sets CDBGPWRUPREQ and waits for CDBGPWRUPACK to indicate the debug clocks are on.
  3. The debugger looks for a main ROM table with the location of all components and other ROM tables.
  4. The debugger compares the peripheral ID of the ROM table against a list of saved system descriptions.
  5. If a description of the system with this ID is saved, the debugger uses that description. Otherwise, the debugger continues with the following steps:
    1. The debugger identifies each component.
    2. The debugger looks up information that is known about that component to determine what interfaces are supported and how to control them for topology detection.
    3. The debugger performs topology detection.
    4. The debugger saves the description for later use.

The ROM tables are a key component of topology detection since they provide the linked list for the debugger to explore.