Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

4.3.4.4.2. MMU-600 TBU Hardware Configurations

The following table shows the different instances of the TBUs and their usage.
Note: The instance names match the names used in this document, the instance names in the RTL may be different.
Table 89.  Managers for TBUs

Instance/Configuration Name

Description

F2H_TBU

TBU for the FPGA-to-HPS bridge

F2SDRAM_TBU

TBU for the FPGA-to-SDRAM bridge

DMA_TBU

TBU for the DMAs

TSN_TBU

TBU for the TSNs

IO_TBU

TBU for the USB 2.0, USB3.1, NAND, SD/eMMC, Debug

SDM_TBU

TBU for the SDM

These are the configuration parameters for the four different configurations.

Table 90.  Different TBU Configurations
Feature Parameter name Description

IO_T

BU/

DMA_

TBU/

SDM_

TBU

TSN_T BU F2SDRA M_TBU F2H _TBU
TBS and TBM interface AXI ID width TBUCFG_ID_WIDTH AXI ID width for the transaction subordinate (TBS) and transaction manager (TBM) interfaces. 8 8 8 8
TBS and TBM interface AXI data width

TBUCFG_DATA_WIDTH

AXI DATA Bus width for TBS and TBM 64 64 256 256

TBS and TBM interface AXI

ReadAddress

USER bus width

TBUCFG_ARUSER_ WIDTH AXI USER bus width for the TBS and TBM interfaces. 25 25 10 10

TBS and TBM interface AXI Write Address

USER bus width

TBUCFG_AWUSER_ WIDTH AXI USER bus width for the TBS and TBM interfaces. 25 25 30 30

TBS and TBM interface AXI

Read Response

USER bus width

TBUCFG_RUSER_WIDTH

AXI USER bus width for the TBS and TBM interfaces. 1 1 1 1

TBS and TBM interface AXI Write data

USER bus width

TBUCFG_WUSER_WIDTH

AXI USER bus width for the TBS and TBM interfaces. 1 1 1 1

TBS and TBM interface AXI Write Response

USER bus width

TBUCFG_BUSER_WIDTH

AXI USER bus width for the TBS and TBM interfaces. 1 1 1 1
TBS interface StreamID width

TBUCFG_SID_WIDTH

StreamID width for the TBS interface. 16 16 16 16
TBS interface SubstreamID width

TBUCFG_SSID_WIDTH

SubstreamID width for the TBS interface. 1 1 1 1

TBS and TBM

interface stash

ID signal

TBUCFG_STASH

Set this parameter to 1 to include stash ID signals for the TBS and TBM interfaces.

1 1 0 1
Write buffer depth

TBUCFG_WBUF_DEPTH

This parameter defines the maximum number of beats that the TBU write data buffer can store. 16 16 16 16
Latency FIFO depth

TBUCFG_LFIFO_DEPTH

Number of entries in the Latency FIFO buffer. 0 0 0 0

Number of translation slots

TBUCFG_XLATE_SLOTS

Number of TBU translation slots. This number controls the number of transactions for which the TBU can perform translations at the same time.

8 8 8 8
Maximum number of read transactions

TBUCFG_ROT_DEPTH

Maximum number of outstanding read transactions that the TBU supports. 16 16 16 16
Maximum number of write transactions

TBUCFG_WOT_DEPTH

Maximum number of outstanding write transactions that the TBU supports. 16 16 16 16
Micro TLB Depth

TBUCFG_UTLB_DEPTH

Number of entries in the Micro TLB. 16 16 16 16
Main TLB Depth

TBUCFG_MTLB_DEPTH

Number of entries in the Main TLB. 64 64 256 128
TBU register Slice

TBUCFG_SI_AR_HN

DSHK_MODE

TBUCFG_SI_R_HND

SHK_MODE

TBUCFG_SI_AW_H

NDSHK_MODE

TBUCFG_SI_W_HN

DSHK_MODE

TBUCFG_SI_B_HND

SHK_MODE

TBUCFG_MI_AR_H

NDSHK_MODE

TBUCFG_MI_R_HN

DSHK_MODE

TBUCFG_MI_AW_H

NDSHK_MODE

TBUCFG_MI_W_HN

DSHK_MODE

TBUCFG_MI_B_HN DSHK_MODE

TBUCFG_DTI_HND

SHK_MODE

You can configure optional TBU TBS, TBM, and DTI interface register slices for improved timing. You can set these parameters to the following values:

  • FULL. Fully registered, double-buffered register slice.
  • FWD. Registered on forward path only, that is, the direction that xVALID on the corresponding interface indicates.
  • REV. Registered on reverse path only, that is, the direction that xREADY on the corresponding interface indicates.
  • BP. Bypass register slice.
3 3 3 3

Main TLB

register slice

TBUCFG_MTLB_LKP RSP_MODE This parameter is ignored but maintained for compatibility with r0p0. Set this parameter to 0. 0 0 0 0
TBU direct indexing

TBUCFG_DIRECT_IDX

Set this parameter to 1 to enable direct indexing for a TBU.

Set this parameter to 0 to disable direct indexing for a TBU, or if TBUCFG_MTLB_DEPTH == 0.

0 0 1 1
Main TLB partitions

TBUCFG_MTLB_PARTS

Number of Main TLB partitions. Set this parameter to 1 if one of the following is true:

  • TBUCFG_MTLB_DEPTH == 0.
  • TBUCFG_DIRECT_IDX

== 1.

1 1 1 1