Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

6.4.1.7. Boot Scratch Space

The boot scratch space contains ten registers on the warm reset domain, ten registers on the cold reset domain, and ten registers on the POR reset domain as shown in the table below.

Table 289.  Boot Scratch Space Registers
Register Name Reset Domain Description
System_Mgr.boot_scratch_por<0:9> 10 32-bit scratch registers on the POR reset domain The register contents will be cleared on an HPS POR reset but will be retained during an HPS cold reset as well as an HPS warm reset.
System_Mgr.boot_scratch_cold<0:9> 10 32-bit scratch registers on the Cold reset domain The register contents will be cleared on an HPS POR reset or an HPS cold reset, but will be retained on an HPS warm reset.
System_Mgr.boot_scratch_warm<0:9> 10 32-bit scratch registers on the Warm reset domain The register contents will be cleared on an HPS POR reset, an HPS cold reset, or an HPS warm reset.