Visible to Intel only — GUID: gak1667328702882
Ixiasoft
Visible to Intel only — GUID: gak1667328702882
Ixiasoft
7. Clock Manager
The hard processor system (HPS) clock generation is centralized in the clock manager. The clock manager is responsible for providing software-programmable clock control to configure all clocks generated in the HPS. Clocks are organized in clock groups. A clock group is a set of clock signals that originate from the same clock source which may be synchronous to each other. The clock manager has two phase-locked loop (PLL) clock group where the clock source is a common PLL voltage-controlled oscillator (VCO). A clock group which is independent and asynchronous to other clocks may only have single clock, also known as clock slice. Peripheral clocks are a group of independent clock slices.
Section Content
Clock Manager Differences Among Intel SoC Device Families
Clock Manager Use Cases
Clock Manager Features
Clock Manager System Integration
Clock Manager Signal Description
Clock Manager Functional Description
Clock Manager Programming Model
Clock Manager Address Map and Register Definitions
Clock Manager Design Guidelines and Examples