Visible to Intel only — GUID: jdg1673544125715
Ixiasoft
Visible to Intel only — GUID: jdg1673544125715
Ixiasoft
A.1. Booting and Configuration
The Secure Device Manager (SDM) in the FPGA manages the hard processor system (HPS) boot and FPGA configuration of the Agilex™ 5 SoC device. Both the HPS boot and FPGA configuration comprise a series of stages that always begins with SDM initialization.
After the Agilex™ 5 SoC device is released from power-on-reset (POR), the SDM manages the initial configuration of the device. All configuration and boot source interfaces are connected to the SDM. The SDM determines and enforces the security level on the device, ensuring the bitstream, which includes the HPS first stage bootloader (FSBL), originate from a trusted source.
You can program the Agilex™ 5 SoC device to configure the FPGA first and then boot the HPS. Alternatively, you can boot the HPS first and then configure the FPGA core as part of the second-stage boot loader (SSBL) or after the Operating System (OS) boots.
The following documents provide a comprehensive guidance on managing the HPS boot, FPGA configuration and security:
Intel® describes configuration schemes from the point-of-view of the FPGA. Agilex™ 5 devices support active and passive configuration schemes. In active configuration schemes the FPGA acts as the master and the external memory acts as a slave device. In passive configuration schemes an external host acts as the master and controls configuration. The FPGA acts as the slave device. All Agilex™ 5 configuration schemes support design security, remote system update (RSU), and partial reconfiguration. To implement remote system update in passive configuration schemes, an external controller must store and drive the configuration bitstream.
Agilex™ 5 devices support the following configuration schemes:
- Avalon® Streaming ( Avalon® -ST)
- JTAG
- Configuration via Protocol (CvP)
- Active Serial (AS) normal and fast modes
Avalon® -ST
The Avalon® -ST configuration scheme is a passive configuration scheme. Avalon® -ST is the fastest configuration scheme for Agilex™ 5 devices. Avalon® -ST configuration supports x8 and x16 bit mode. The x8 bit mode uses dedicated SDM I/O pins. The x16 mode uses general-purpose I/Os (GPIOs) for configuration.
Avalon® -ST supports backpressure using the AVST_READY and AVST_VALID pins. Because the time to decompress the incoming bitstream varies, backpressure support is necessary to transfer data to the Agilex™ 5 device. For more information about the Avalon® -ST, refer to the Avalon® Interface Specifications.
JTAG
You can configure the Agilex™ 5 device using the dedicated JTAG pins. The JTAG port provides seamless access to many useful tools and functions. In addition to configuring the Agilex™ 5, the JTAG port is used for debugging with Signal Tap or the System Console tools.
The JTAG port has the highest priority and overrides the MSEL pin settings. Consequently, you can configure the Agilex™ 5 device over JTAG even if the MSEL pin specify a different configuration scheme unless you disabled JTAG for security reasons.
CvP
CvP uses an external PCIe* host device as a Root Port to configure the Agilex™ 5 device over the PCIe* link. You can specify up to a x8 PCIe* link. Typically, the bitstream compression ratio and the SDM input buffer data rate, not the PCIe* link, limit the configuration data rate. Agilex™ 5 devices support two CvP modes, CvP init and CvP update.
- CvP configures the FPGA periphery image which includes I/O information and hard IP blocks, including the PCIe* IP. Because the PCIe* IP is in the periphery image, PCIe* link training establishes the PCIe* link of the CvP PCIe* IP before the core fabric configures.
- The host device uses the CvP PCIe* link to configure your design in the core fabric.
- Allows reprogramming of the core to run different algorithms.
- Provides a mechanism for standard updates as a part of a release process.
- Customizes core processing for different components that are part of a complex system.
For both CvP Init and CvP Update modes, the maximum data rate depends on the PCIe* generation and number of lanes.
For Agilex™ 5 SoC devices, CvP is only supported in FPGA configuration first mode.
AS Normal Mode
Active Serial x4 or AS x4 or Quad SPI is an active configuration scheme that supports flash memories capable of three- and four-byte addressing. Upon power up, the SDM boots from a boot ROM which uses three-byte addressing to load the configuration firmware from the Quad SPI flash. After the configuration firmware loads, the Quad SPI flash operates using four-byte addressing for the rest of the configuration process.
AS Fast Mode
The only difference between AS normal mode and AS fast mode is speed. Use AS fast mode when configuration timing is a concern. Use this mode to meet the 100 ms of power up requirement for PCIe* or for other systems with strict timing requirements.
In AS fast mode, the SDM first powers the external AS x4 flash. The power supply must be able to provide an equally fast ramp up for the Agilex™ 5 device and the external AS x4 flash devices. Failing to meet this requirement causes the SDM to assume the memory is missing. Consequently, configuration fails.