Visible to Intel only — GUID: qlu1677623550091
Ixiasoft
Visible to Intel only — GUID: qlu1677623550091
Ixiasoft
4.1.5.4.2.2. Address Map When Using Multiple SDRAM Channels
When using 2 or 4 SDRAM channels, all SDRAM traffic must be interleaved between DMI0 and DMI1 on a 4K basis. The address map for this configuration is shown below.
In the center column, the SDRAM space is shown with alternating green and red stripes, representing 4K address regions where A[12] is ‘0’ (green) and A[12] is ‘1’ (red). The CCU forwards the traffic to either DMI0 or DMI1 without modifying the associated address. This means that the address map for DMI0 and DMI1 show gaps where the traffic is routed to the other port. In this case, there is a single memory interleave group (MIG0) that contains DMI0 and DMI1, and a single memory interleave group set (MIGS0) that contains MIG0. MIGS0 = [{DMI0, DMI1}].