Visible to Intel only — GUID: afr1679308880099
Ixiasoft
Visible to Intel only — GUID: afr1679308880099
Ixiasoft
15.5.7.6. CoreSight* Debug and Trace Resets
The following table lists all the CoreSight* debug and trace resets.
Clock Name | Destination | Description |
---|---|---|
por_rst_n | CoreSight SWJ-DP porst_n input |
POR is the main source to reset the JTAG clock domain. |
tap_rst_n | CoreSight SWJ-DP ntrst input |
ntrst is driven by the ntrst pin ANDed with POR, but the ntrst pin is not supported so tap_rst_n is driven by POR only. Alternatively, force the TAP controller into the Test-Logic-Reset (TLR) state. |
dbg_rst_n | All CoreSight debug and trace blocks, including the DebugBlock but not the DSU |
The debug reset connects to all debug logic in the cs_at_clk, cs_pdbg_clk, and cs_trace_clk domains.
Note: This does not connect to the DSU nPRESET and nATRESET inputs.
|
l2_rst_n | DSU | The functional l2_rst_n reset connects to the DSU nPRESET and nATRESET inputs. |
l3_rst_n | Generic Timer TSGEN | Generic timer which is customizable by customer. |