Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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2.2.9.5. Watchdog Timers

The HPS provides four watchdogs connected to the L4 buses in addition to the watchdogs built into the MPU. The four watchdog timers have a 32-bit timer resolution and are based on the Synopsys® DesignWare* APB* Watchdog Timer peripheral.

A watchdog timer can be programmed to generate a reset request on a timeout. Alternatively, the watchdog can be programmed to assert an interrupt request on a timeout, and if the interrupt is not serviced by software before a second timeout occurs, generate a reset request.