Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

25. CoreSight Debug and Trace

CoreSight systems provide all the infrastructure you require to debug, monitor, and optimize the performance of a complete HPS design. CoreSight technology addresses the requirement for a multi-core debug and trace solution with high bandwidth for whole systems beyond the processor core.

CoreSight technology provides the following features:

  • Cross-trigger support between SoC subsystems
  • High data compression
  • Multi-source trace in a single stream
  • Standard programming models for standard tool support

The hard processor system (HPS) infrastructure provides visibility and control of the HPS modules, the ARM® Cortex-A53 MPCore processor, and user logic implemented in the FPGA fabric. The debug system design incorporates ARM® CoreSight* components.

Details of the ARM® CoreSight* debug components can be viewed by clicking on the following related information links: