Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.5.12. Cache Protection

The L1 instruction cache provides parity checking with single error detection (SED). Double bit errors are not detected or corrected.

The L1 data cache and L2 cache provide single error correction and double error detection (SECDED). If a single-bit error is detected, the access that caused the error is stalled while the correction takes place. After correction, the access that was stalled continues or is retried.

Correction behavior varies depending on RAM type.
Table 34.  Cache Protection Behavior
RAM Protection Type Protection Granule Correction Behavior
L1 Instruction cache tag Parity, SED 31 bits Both lines in the cache set are invalidated, and then the line requested is refetched from L2 cache or external memory.
L1 Instruction cache data Parity, SED 20 bits Both lines in the cache set are invalidated, and then the line requested is refetched from L2 cache or external memory.
TLB Parity, SED 52 bits The entry is invalidated, and a new pagewalk is started to refetch it.
L1 Data cache tag Parity, SED 32 bits The line is cleaned and invalidated from the L1 cache. SCU duplicate tags are used to get the correct address. The line is refetched from L2 cache or external memory.
L1 Data cache data ECC, SECDED 32 bits The line is cleaned and invalidated from the L1 cache, with single bit errors corrected as part of the eviction. The line is refetched from L2 cache or external memory.
L1 data cache dirty bit Parity, SED with correction by re-loading data 1 bit The line is cleaned and invalidated from the L1 cache, with detection of dirty bit corruption through parity checking. Only the dirty bit is protected. The other bits are performance hints, therefore do not cause a functional failure if they are incorrect. Error is corrected by reloading the data.
SCU L1 duplicate tag ECC, SECDED 33 bits The tag is rewritten with the correct value, and the access is retried. If the error is uncorrectable then the tag is invalidated.
L2 tag ECC, SECDED 33 bits The tag is rewritten with the correct value, and the access is retried. If the error is uncorrectable then the tag is invalidated.
L2 data ECC, SECDED 64 bits Data is corrected inline, and the access might stall for an additional cycle or two while the correction takes place. After correction, the line might be evicted from the processor.