Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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2.2.4. System Memory Management Unit

The SMMU provides system-wide address translation for system bus masters. A two-stage translation supports memory virtualization. The module includes a single TCU that controls distributed translation buffer units (TBUs).

The system MMU features include:

  • A central TCU that supports five distributed TBUs for the following masters:
    • FPGA
    • DMA
    • EMAC0-2, collectively
    • USB0-1, NAND, SD/MMC, ETR, collectively
    • Secure Device Manager (SDM)
  • Caches for storing page table entries and intermediate table walk data:
    • 512-entry macro translation lookaside buffer (TLB) page table entry cache in the TCU
    • 128-entry micro TLB for table walk data in the FPGA TBU and 32-entry micro TLB for all other distributed TBUs
    • Single-bit error detection and invalidation on error detection for caches
  • Communication with the MMU of the ARM® Cortex® -A53 MPCore™
  • System-wide address translation
  • Address virtualization
  • Support for 32 contexts
  • Two stages of translation or combined (stage 1 and stage 2) translation
  • Support for up to 49-bit virtual addresses and up to 48-bit physical and intermediate physical addresses
  • Programmable QoS to support page table walk arbitration
  • Fault handling, logging and interrupts for translation errors
  • Debug support