Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.5.16. Cache Coherency Unit

The Cache Coherency Unit (CCU) resides outside of the Cortex® -A53 MPCore™ processor and maintains data coherency within the SoC system. Masters in the system, including HPS peripheral and user logic in the FPGA, can access coherent memory through the CCU. The FPGA interfaces to the CCU through the FPGA-to-HPS bridge.

The CCU provides I/O coherency. I/O coherency, also called one-way coherency, allows a CCU master to see the coherent memory visible to the Cortex® -A53 processor but does not allow the Cortex® -A53 processor to see memory changes outside of its cache.

The masters that communicate with the CCU can read coherent memory from the L1 and L2 caches, but cannot write directly to the L1 cache. If a master performs a cacheable write to the CCU, the L2 cache updates. Any of the cacheable write locations that reside in the L1 data cache are invalidated because the L2 cache has the latest copy of those addresses.

The CCU communicates with the SCU within the Cortex® -A53 MPCore™ to provide coherency with the SCU.

For more information, please refer to the Cache Coherency Unit Chapter.