Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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15.4.9. Data DMA

The DMA transfers data with minimal host involvement. Software initiates data DMA with the MAP10 command.

The flag bit of the dma_enable register in the dma group enables data DMA functionality. Only enable or disable this functionality when there are no active transactions pending in the NAND flash controller. When the DMA is enabled, the flash controller initiates one DMA transfer per MAP10 command over the DMA master interface. When the DMA is disabled, all operations with the flash controller occur through the memory-mapped nanddata region.

The NAND flash controller supports up to four outstanding DMA commands, and ignores additional DMA commands. If software issues more than four outstanding DMA commands, the flash controller issues the unsup_cmd interrupt. On receipt of a DMA command, the flash controller performs command sequencing to transfer the number of pages requested in the DMA command. The DMA master reads or writes page data from the system memory in programmed burst‑length chunks. After the DMA command completes, the flash controller issues an interrupt, and starts working on the next queued DMA command.

Pipelining allows the NAND flash controller to optimize its performance while executing back‑to‑back commands of the same type.

With certain restrictions, non‑DMA MAP10 commands can be issued to the NAND flash controller while the flash controller is servicing DMA transactions. MAP00, MAP01, and MAP11 commands cannot be issued while DMA mode is enabled because the flash controller is operating in an extremely tightly‑coupled, high‑performance data transfer mode. On receipt of erroneous commands (MAP00, MAP01 or MAP11), the flash controller issues an unsup_cmd interrupt to inform the host about the violating command.

Consider the following points when using the DMA:

  • A data DMA command is a type of MAP10 command. This command is interpreted by the data DMA engine and not by the flash controller core.
  • No MAP01, MAP00, or MAP11 commands are allowed when DMA is enabled.
  • Before the flash controller can accept data DMA commands, DMA must be enabled by setting the flag bit of the dma_enable register in the dma group.
  • When DMA is enabled and the DMA engine initiates data transfers, ECC can be enabled for as‑needed data correction concurrent with the data transfer.
  • MAP10 commands are used along with data movements similar to MAP01 commands.
  • With the exception of data DMA commands and MAP10 pipeline read and write commands, all other MAP10 commands such as erase, lock, unlock, and copy‑back are forwarded to the flash controller.
  • At any time, up to four outstanding data DMA commands can be handled by flash controller. During multi‑page operations, the DMA transfer must not cross a flash block boundary. If it does, the flash controller generates an unsupported command (unsup_cmd) interrupt and drops the command.
  • Data DMA commands are typically multi‑page read and write commands with an associated pointer in host memory. The multi‑page data is transferred to or from the host memory starting from the host memory pointer.
  • Data DMA uses the flash_burst_length register in the dma group to determine the burst length value to drive on the interconnect. The data DMA hardware does not account for the interconnect’s boundary crossing restrictions. The host must initialize the starting host address so that the DMA master burst transaction does not cross a 4 KB boundary.

There are two methods for initiating a DMA transaction: the multi-transaction DMA command, and the burst DMA command.