Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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4.5.5.2.1. Rate Limiter Configuration

Enable transfer rate limiters by setting the Rate Limit Logic Enable bit of the Streaming TX Rate Limiter (btrl) register. The rate limiter configuration register (per transmit interface) has the following fields:
Table 43.  TX Rate Limiter Fields
Bits Name Description
31:21 Reserved Reserved
20 Rate Limit Logic Enable Setting this bit enables the rate limiter logic that arbitrates master transfers.
19:16 Token Bucket Size Program this field to indicate the maximum number of tokens that may accumulate at an interface when rate limiters are enabled.
15:0 Rate Limit Value (N)

Program this field to indicate the peak rate limit for traffic from the host interface to the coherency interconnect. If the value N represents the rate limit value, then the rate equation is:

rate=N/(216)

The rate limit value(N) is a 16-bit adder where the overflow bit is the token arrival bit.

For example, if you want to specify a rate of 1 token every 5 cycles (or 20%), program N to be 13107 (decimal) or 0x3333. When added together 5 times, the value is approximately 216, so one packet can be sent every 5 cycles.

Note: If you dynamically change the Streaming TX Rate Limiter (btrl) register values while the Rate Limit Logic Enable bit is set and master transactions are active, the rate behavior is nondeterministic for a short period.