Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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16.4.4. Clocks

Clocking Architecture

The clocking architecture is composed of:
Table 143.  Clocking Architecture
Clock Name Source IP Clock Name Range Description
l4_mp_clk Clock Manager clk 200 MHz System, host, AHB clock
sdmmc_clk Wrapper Generated cclk_in 50 MHz Card interface unit (CIU) clock
cclk_in_drv (phase shifted cclk_in) Phase-shifted/delayed version of cclk_in on which output-related registers work.
cclk_in_sample (phase shifted cclk_in Phase-shifted/delayed version of cclk_in used for sampling the data from the card.
Synopsys IP Generated cclk_out Synopsys IP Generated Card clocks. Output from internal clock dividers.

Clock Generation

The phase shift block is required for the following actions:
  • To divide the 200 MHz sdmmc_clk input by 4 to generate a 50 MHz clock
  • To generate 0, 45, 90, 135, 180, 225, 270 and 315 degree phase shifts of a 50 MHz clock
The System Manager provides software controlled selects, drv_sel[2:0] and smpl_sel[2:0], to control the phase shifts for the cclk_in_drv and cclk_in_sample, respectively.
Figure 61. SD/MMC Controller Clock Connections - HPS