Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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B.5.7. Configuring the Flash Device

For read and write accesses, software must initialize the device read instruction register (devrd) and the device write instruction register (devwr). These registers include fields to initialize the instruction opcodes that should be used as well as the instruction type, and whether the instruction uses single, dual or quad pins for address and data transfer. To ensure the quad SPI controller can operate from a reset state, the opcode registers reset to opcodes compatible with single I/O flash devices.

The quad SPI flash controller uses the instruction transfer width field (instwidth) of the devrd register to set the instruction transfer width for both reads and writes. There is no instwidth field in the devwr register. If instruction type is set to dual or quad mode, the address transfer width (addrwidth) and data transfer width (datawidth) fields of both registers are redundant because the address and data type is based on the instruction type. Thus, software can support the less common flash instructions where the opcode, address, and data are sent on two or four lanes. For most instructions, the opcodes are sent serially to the flash device, even for dual and quad instructions.