Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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10.4.4.4.1. Register Interface Tests

You can correct memory errors and test the memory register interface through registers in the ECC Controller.

The following registers can be used to test and correct memory:
  • ECC_Addrbus: Holds the address of the memory and ECC data.
  • ECC_RData3bus through ECC_RData0bus: Holds memory data from a read access.
  • ECC_WData3bus through ECC_WData0bus: Holds the data to be written to memory.
  • ECC_RDataecc1bus and ECC_RDataecc0bus: Holds the ECC data from a read access.
  • ECC_WDataecc1bus and ECC_WDataecc0bus: Holds the ECC data to be written to memory.
  • ECC_accctrl: Configures the access as a read or a write and enables memory and ECC data overwrites.
  • ECC_startacc: Initiates the register interface access of memory data or ECC data.

Single-Bit Error Test for DMA ECC RAM

This sequence tests the single-bit error detection and correction in the ECC decoder of the DMA ECC RAM.
  1. Write data to the ECC_WData3bus through ECC_WData0bus registers.
  2. Set the ECC_EN bit in the CTRL register to enable the ECC detection and correction logic.
  3. Set the DBEN bit in the ECC_dbytectrl register.
  4. Select the address bus to write the data to by programming the ECC_Addrbus register.
  5. In the ECC_accctrl register, program the following bits:
    • RDWR=1
    • ECCOVR=0
    • DATAOVR=1
  6. Set the ENBUS* bit in the ECC_startacc register to trigger an indirect write access.
  7. Clear the ECC_EN bit in the CTRL register to disable the ECC detection and correction logic.
  8. Write a data value that has one bit altered in the ECC_WData3bus through ECC_WData0bus registers to the same address.
  9. Set the ENBUS* bit in the ECC_startacc register to trigger an indirect write access.
  10. In the ECC_accctrl register, program the following bits:
    • RDWR=0
    • ECCOVR=1
    • DATAOVR=1
  11. Set the ECC_EN bit in the CTRL register to enable the ECC detection and correction logic.
  12. Set the ENBUS* bit in the ECC_startacc register to trigger an indirect write access.
    If you have configured an interrupt to trigger for a single-bit error, then expect it to trigger after these steps have completed. If you read back the data at the same address using the ECC_RData*bus register, expect to see a corrected data result from the memories.

Single-Bit Error Test for Word-Writeable Memories

This sequence tests the single-bit error detection and correction in the ECC decoder of the word-writeable ECC RAMs.
  1. Write data to the ECC_WData3bus through ECC_WData0bus registers.
  2. Set the ECC_EN bit in the CTRL register to enable the ECC detection and correction logic.
  3. Set the DBEN bit in the ECC_dbytectrl register.
  4. Select the address bus to write the data to by programming the ECC_Addrbus register.
  5. In the ECC_accctrl register, program the following bits:
    • RDWR=1
    • ECCOVR=0
    • DATAOVR=1
  6. Set the ENBUS* bit in the ECC_startacc register to trigger an indirect write access.
  7. In the ECC_accctrl register, program the following bits:
    • RDWR=0
    • ECCOVR=1
    • DATAOVR=0
  8. Set the ENBUS* bit in the ECC_startacc register to trigger an indirect write access.
  9. Write a data value that has one bit altered in the ECC_WData3bus through ECC_WData0bus registers to the same address.
  10. Read the resultant data from the ECC_RDataecc*bus registers at the same address.
  11. Write the value from the ECC_RDataecc*bus registers into the ECC_WDataecc*bus registers.
  12. In the ECC_accctrl register, program the following bits:
    • RDWR=1
    • ECCOVR=1
    • DATAOVR=1
  13. Set the ENBUS* bit in the ECC_startacc register to trigger an indirect write access.
  14. In the ECC_accctrl register, program the following bits:
    • RDWR=0
    • ECCOVR=1
    • DATAOVR=1
  15. Set the ENBUS* bit in the ECC_startacc register to trigger an indirect write access.
    If you have configured an interrupt to trigger for a single-bit error, then expect it to trigger after these steps have completed. If you read back the data at the same address using the ECC_RData*bus register, expect to see a corrected data result from the memories.

Double-Bit Error Test

This sequence tests the double-bit error detection in the ECC decoder.
  1. Enable the ECC by setting the ECC_EN bit in the CTRL register.
  2. Set the Data override (DATAOVR) bit in the ECC_accctrl register.
  3. Write data to an address location in memory using a normal memory write. The correct ECC data should be generated.
  4. Write a data value that has two bits altered in the ECC_WData3bus through ECC_WData0bus registers and write the address of the memory location in the ECC_Addrbus.
  5. Configure the ECC_accctrl register to a write and set the ENBUSA bit of the ECC_startacc register to initiate the write. If the memory is dual-ported, an ENBUSB bit could optionally be enabled depending on the port access.
  6. Read the same memory location using a normal memory read access. Expect a double-bit error to be logged without data correction. Refer to the Error Logging section for more details about identifying errors.