Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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11.2. Top Level Clocks

Figure 39. Clock Manager Block Diagram
The Clock Manager contains 2 PLLs, the Main PLL and Peripheral PLL. Inputs into these two PLLs can come from the input pin HPS_OSC_CLK, the internal oscillator, cb_intosc_div2_clk or the f2s_free_clk FPGA clock input.
Note: You cannot use the internal oscillator under normal working stages, because its accuracy is not high enough, which means you can only use it to bring up the HPS.
Both PLLs generate 9 clock outputs to be used by the output clock blocks shown in the diagram. Output clock blocks include the MPU clock block, the NOC clock block and the peripheral clock block. The peripheral clock block is comprised of GPIO, EMAC, SDMMC, and HPS-to-FPGA clocks.
The clock from each of these output clock blocks is sourced from either the bypass clock (boot_clk) or a non-bypass clock. A non-bypass clock can be one of five sources.
Table 94.  Non-Bypass Clock Sources
Source Description
HPS_OSC_CLK Pin for external oscillator (selected from one of the 48 HPS Dedicated I/O)
f2h_free_clock (25 MHz - 125 MHz) FPGA fabric PLL clock reference
cb_intosc_div2_clk Internal ring oscillator divided by 2 (230 MHz maximum)
PLL0 Counter Output Main PLL counter outputs 0 to 9
PLL1 Counter Output Peripheral PLL counter outputs 0 to 9
Table 95.  Top Level Clocks
Clock Name Source/Destination Description
mpu_free_clk Clock manager To MPU complex Source clock from clock manager for both the MPU clock groups.
mpu_clk Internal to MPU complex MPU main clock
mpu_ccu_clk Main clock for CCU. Internal to MPU Complex and HMC switch in NOC. MPU L2 RAM Clock and HMC switch in NOC. Fixed at ½ mpu_clk.
mpu_periph_clk Internal to MPU complex MPU peripherals clock for interrupts, timers, and watchdogs. Fixed at ¼ mpu_clk.
l3_main_free_clk Clock manager to NOC/Peripherals Interconnect L3 main switch clock. Always free running.
l4_sys_free_clk Clock manager to NOC/Peripherals Interconnect L4 system clock. Always free running.
l4_main_clk Clock manager to NOC/Peripherals L4 Interconnect clock for fast peripherals including DMA, SPIM, SPIS and TCM.
l4_mp_clk Clock manager to NOC/Peripherals Interconnect L4 peripheral clock for peripherals including NAND, USB, and SDMMC.
l4_sp_clk Clock manager to NOC/Peripherals Interconnect L4 slow peripheral clock for peripherals including Timer, I2C, and UART.
cs_at_clk Clock manager to CoreSight/NOC CoreSight Trace clock and Debug time stamp clock.
cs_pdbg_clk Clock manager to CoreSight CoreSight bus clock
cs_trace_clk Clock manager to CoreSight

CoreSight Trace I/O clock. This is independent and defaults to a low frequency (25 MHz) for lower speed debuggers.

cs_timer_clk Clock manager to CoreSight/NOC

CoreSight timer clock. Same as cs_at_clk with different software enable to ensure MPU clock running.

h2f_user_clk0 HPS to FPGA fabric General purpose interface clock to FPGA.
h2f_user_clk1 HPS to FPGA fabric General purpose interface clock to FPGA.