Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.5.3.1. Translation Lookaside Buffers

Each CPU in the Cortex® -A53 MPCore™ contains micro and main translation lookaside buffers (TLBs).
Table 32.  MMU Features of Each CPU in the Cortex® -A53 MPCore™

TLB Type

Memory Type

Number of Entries

Associativity

Micro TLB

Instruction

10

Fully associative

Micro TLB

Data

10

Fully associative

Main TLB

Instruction and Data

512

Four-way set-associative

Each CPU also includes:
  • 4-way set associative 64-entry walk cache that holds the result of a stage 1 translation. The walk cache holds entries fetched from the secure and non-secure state.
  • 4-way set associative 64-entry intermediate physical address (IPA) cache. This cache holds map points between intermediate physical addresses and physical addresses. Only non-secure exception level 1 (EL1) and exception level 0 (EL0) stage 2 translations use this cache.
TLB entries include global and application specific identifiers to prevent context switch TLB flushes. The architecture also supports virtual machine identifiers (VMIDs) to prevent TLB flushes on virtual machine switches by hypervisor.

The micro TLBs are the first level of caching for the translation table information. The unified main TLB handles misses from the micro TLBs.

When the main TLB performs maintenance operations it flushes both the instruction and data micro TLBs.