Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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24.3.3. Watchdog Timers Clocks

Each watchdog timer is connected to the l4_sys_free_clk clock so that timer operation is not dependent on the phase-locked loops (PLLs) in the clock manager and so that it is always running. This independence allows recovery from software that inadvertently programs the PLLs in the clock manager incorrectly.

Table 213.  Watchdog Timers Clocks
Timers System Clock
watchdog0 l4_sys_free_clk
watchdog1 l4_sys_free_clk
watchdog2 l4_sys_free_clk
watchdog3 l4_sys_free_clk