Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

6.1.1. System Interconnect Block Diagram and System Integration

The system interconnect consists of connection points, datapaths, and the service network.
  • Connection points interface the NoC to masters and slaves of other HPS components
  • Datapath switches transport data across the network, from initiator connection points to target connection points
  • Service network allows you to update master and slave peripheral security features and access NoC registers
The system interconnect is a tiered system, divided into the following domains:
  • L3 interconnect: moves high-bandwidth data between masters and slaves in the HPS.
  • L4 buses: lower performance than the L3 interconnect. These buses connect mid-to-low performance peripherals.

The interconnect is also connected to the Cache Coherency Unit (CCU). The CCU provides additional routing between the MPU, FPGA-to-HPS bridge, L3 interconnect, and SDRAM L3 interconnect.

In addition to providing routing connectivity and arbitration between masters and slaves in the HPS, the NoC features firewall security, QoS mechanisms, and observation probe points throughout the interconnect.