Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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23.2. Timers Block Diagram and System Integration

Each timer includes a slave interface for control and status register (CSR) access, a register block, and a programmable 32‑bit down counter that generates interrupts on reaching zero. The timer operates on a single clock domain driven by the clock manager.
Figure 137. Timers Block Diagram