Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.1.1.2.1. Stratix 10 HPS Master-to-Slave Connectivity Matrix

The system interconnect is a highly efficient packet-switched network.

The following table shows the connectivity of all the master and slave interfaces in the system interconnect.

Table 56.  Master-to-Slave Connectivity
Slaves Masters
DAP CCU Master 2 DMAC 3 EMAC 0/1/2 Peripheral Master 4
CCU Slaves 5  
TCU      
L4 Main Bus Slaves    
L4 MP Bus Slaves      
L4 AHB Bus Slaves      
L4 SP Bus Slaves    
L4 SYS Bus Slaves    
Secure/Non-Secure Timestamp System Counters    
L4 ECC Bus Slaves      
DAP    
STM      
Lightweight HPS-to-FPGA Bridge
HPS-to-FPGA Bridge
Service Network      
HPS-to-SDM – Peripheral Access (QSPI, NAND, SDMMC)    
HPS-to-SDM – Mailbox Access      
2 CCU Master Agent: Cortex-A53 MPCore, FPGA-to HPS, HPS peripheral masters, TCU
3 Direct Memory Access Controller
4 Peripheral Master TBU, including:
  • TBU for EMAC 0/1/2
  • TBU for USB 0/1, NAND, SD/MMC, and ETR
  • TBU for DMAC
5 CCU Slaves: External SDRAM Memory, SDRAM registers, on-chip RAM, GIC, HPS peripheral slaves