Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

18.1. Features of the USB OTG Controller

The USB OTG controller has the following USB‑specific features:

  • Complies with both Revision 1.3 and Revision 2.0 of the On The Go and Embedded Host Supplement to the USB Revision 2.0 Specification
  • Supports software‑configurable modes of operation between OTG 1.3 and OTG 2.0
  • Can operate in Host or Device mode
  • Supports multi-point applications with hub and split support
  • Supports all USB 2.0 speeds:
    • High speed (HS, 480‑Mbps)
    • Full speed (FS, 12‑Mbps)
    • Low speed (LS, 1.5‑Mbps)
      Note: In host mode, all speeds are supported. However, in device mode, only high speed and full speed are supported.
  • Integrated scatter-gather DMA supports moving data between memory and the controller
  • Supports USB 2.0 in ULPI mode
  • Supports all USB transaction types:
    • Control transfers
    • Bulk transfers
    • Isochronous transfers
    • Interrupts
  • Supports automatic ping capability
  • Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
  • Supports suspend, resume, and remote wake
  • Supports up to 16 host channels
    Note: In host mode, when the number of device endpoints is greater than the number of host channels, software can reprogram the channels to support up to 127 devices, each having 32 endpoints (IN + OUT), for a maximum of 4,064 endpoints.
  • Supports up to 16 bidirectional endpoints, including control endpoint 0
    Note: Only seven periodic device IN endpoints are supported.
  • Supports a generic root hub
  • Performs transaction scheduling in hardware

On the USB PHY layer, the USB OTG controller supports the following features:

  • ULPI PHY support for unidirectional or bidirectional 8-bit SDR bus interface
  • A single USB port connected to each OTG instance
  • A ULPI connection to an off‑chip USB transceiver
  • Software‑controlled access, supporting vendor‑specific or optional PHY registers access to ease debug
  • The OTG 2.0 support for Attach Detection Protocol (ADP) only through an external (off‑chip) ADP controller

On the integration side, the USB OTG controller supports the following features:

  • Different clocks for system and PHY interfaces
  • Dedicated TX FIFO buffer for each device IN endpoint in direct memory access (DMA) mode
  • Packet‑based, dynamic FIFO memory allocation for endpoints for small FIFO buffers and flexible, efficient use of RAM that can be dynamically sized by software
  • Ability to change an endpoint's FIFO memory size during transfers
  • Clock gating support during USB suspend and session‑off modes
    • PHY clock gating support
    • System clock gating support
  • Data FIFO RAM clock gating support
  • Local buffering with error correction code (ECC) support
Note: The USB OTG controller does not support the following protocols:
  • Enhanced Host Controller Interface (EHCI)
  • Open Host Controller Interface (OHCI)
  • Universal Host Controller Interface (UHCI)