Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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2.2.10.4. UARTs

The HPS provides two UART controllers to provide asynchronous serial communications:
  • 16550-compatible UART
  • Support automatic flow control as specified in 16750 standard
The two UART controllers are based on Synopsys® DesignWare* APB* Universal Asynchronous Receiver/ Transmitter peripheral and offer the following features:
  • Direct access for host processor
  • DMA controller may be used for large transfers
  • Separate thresholds for DMA request and handshake signals to maximize throughput
  • 128-byte transmit and receive FIFO buffers
  • Programmable baud rate up to 6.25 MBaud (with 100MHz reference clock)
  • Programmable character properties, such as number of data bits per character (5-8), optional parity bit (with odd or even select) and number of stop bits (1, 1.5 or 2)