Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

15.1. NAND Flash Controller Features

The NAND flash controller provides the following functionality and features:
  • Supports Open NAND Flash Interface (ONFI) 1.0
  • Provides support for 8- and 16-bit flash devices
  • Provides support for up to four chip selects
    Note: Only the first chip select is exposed to the HPS I/O.
  • Supports pipeline read-ahead and write commands for enhanced read and write throughput
  • Supports devices with 32, 64, 128, 256, 384, or 512 pages per block
  • Supports multi-plane devices
  • Supports up to 50 MHz flash operating frequency
  • Provides programmable access timing
  • Supports page sizes of 512 bytes, 2 KB, 4 KB, or 8 KB
  • Supports single layer cell (SLC) and multiple layer cell (MLC) devices with programmable correction capabilities
  • Provides internal direct memory access (DMA)
  • Supports error correction codes (ECCs) providing single-bit error correction and double-bit error detection, with:
    • Sector size programmable 512 byte (4-, 8-, or 16-bit correction) or 1024 byte (24-bit correction)
    • Three NAND FIFOs - ECC Buffer, write FIFO and read FIFO