Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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21.3. UART Controller Signal Description

Table 207.  UART Controller Interface Signals (Routed to HPS I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
UART<1:0>_RX 1 Input Serial input 1'b1 Pull-up
UART<1:0>_TX 1 Output Serial output Pull-up
UART<1:0>_CTS 1 Input Clear to send. When this signal is active, flow control allows UART_TXD 1'b0 Pull-down
UART<1:0>_RTS 1 Output Request to send
Table 208.  UART Controller Interface Signals (Routed to FPGA I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
uart<1:0>_rx 1 Input Serial input 1'b1 Pull-up
uart<1:0>_tx 1 Output Serial output Pull-up
uart<1:0>_cts_n 1 Input Clear to send. When this signal is active, flow control allows UART_TXD 1'b0 - Set Active Pull-down
uart<1:0>_rts_n 1 Output Request to send
uart<1:0>_dsr_n 1 Input Data set ready. Device at other end is ready to communicate. 1'b0 - Set Active Pull-down
uart<1:0>_dcd_n 1 Input Data carrier detect. The “modem” is connected to another “modem” with the carrier detected. 1'b0 - Set Active Pull-down
uart<1:0>_ri_n 1 Input Ring indicator. This indicates that the telephone is ringing, 1'b1 - Set Inactive Pull-up
uart<1:0>_dtr 1 Output Data terminal ready
uart<1:0>_out1_n 1 Output User defined output 1
uart<1:0>_out2_n 1 Output User defined output 2
s2f_uart<1:0>_irq 1 Output interrupt