Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.2.8.1.2. Stratix 10 HPS Slave Security

The system interconnect enforces security through the slave settings. The slave settings are controlled by the NoC Security Control Register (SCR) in the service network.

Firewalls protect certain L3 and L4 slaves. Each of these slaves has its own security check and programmable security settings. After reset, every slave of the system interconnect is in a secure state. This feature is called "boot secure". Only secure masters can access secure slaves.

The NoC implements five firewalls to check the security state of each slave, as listed in the following table. At reset time, all firewalls default to the secure state.

Table 68.  NoC FirewallsThe main system interconnect contains firewalls configured as shown in the following table.
Name Function
l4_per_fw  
l4_sys_fw  
Lightweight HPS-to-FPGA Firewall Controls access through the lightweight HPS-to-FPGA bridge
soc2fpga_fw  
TCU Firewall Controls access to the TCU. The system interconnect interfaces to the TCU through a 64-bit AXI bus.
DAP Firewall Controls access to the CoreSight APB DAP
Peripherals Firewall Filter access to slave peripherals (SPs) in the following buses:
  • L4 main bus
  • L4 master peripherals bus
  • L4 AHB bus
  • L4 slave peripherals bus
System Firewall Filter access to system peripherals in the following components:
  • L4 system bus
  • L4 ECC bus
  • DAP
  • System Trace Macrocell (STM)
  • L4 hard memory controller (HMC)
  • L4 bus registers (SCR firewall, probes, and scheduler)
HPS-to-FPGA Firewall Filter access to FPGA through the HPS-to-FPGA bridge.
DDR and DDR L3 Firewalls Filter access to DDR SDRAM

In addition to the firewalls listed above, the following slaves are protected by firewalls implemented outside the system interconnect:

Table 69.  Firewalls Outside the System Interconnect
Slave Name Comment
DDR Scheduler and HMC Configuration Register Firewall in SDRAM interconnect
Cache Coherency Unit Register Bus (Regbus) Only accessible by Privileged & Secure Transaction
On-chip RAM Module - 256KB Firewall in CCU

At reset, the privilege filters are configured to allow certain L4 slaves to receive only secure transactions. Software must either configure bridge secure at startup, or reconfigure the privilege filters to accept non-secure transactions.

To change the security state, you must perform a secure write to the appropriate SCR register of a secure slave. A non-secure access to the SCR register of a secure slave triggers a bus error.

The following slaves are not protected by firewalls:

Table 70.  Slaves Without Firewalls
Slave Name Comment
GIC The GIC implements its own security extensions
STM STM implements its own master security through master IDs
L4_GENTS (Generic Time Stamp) Fixed Secure/Non-Secure by interconnect, no configuration required.