Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.5.6. Snoop Control Unit

The Snoop Control Unit (SCU) maintains L1 data cache coherency between the four CPUs within the Cortex® -A53 MPCore™ processor.
  • When the processors are set to SMP mode, the SCU maintains data cache coherency between the processors.
    Note: The SCU does not maintain coherency of the instruction caches.
  • The SCU reduces latency by using buffers to execute cache-to-cache transfers between CPUs without accessing external memory.
  • The SCU can accept up to eight requests from the system.

The SCU communicates with the system-level cache coherency unit (CCU) to maintain coherency between the two modules.