Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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7.3.3.1. FPGA-to-HPS CCU to SDRAM/OCRAM Memory (Cache Non-Allocate)

If your logic issues a Cache Non-Allocate transaction, the CCU maintains coherency but does not allocate in the cache. This is useful when you want to maintain coherency but not thrash the cache.

Reads

  • On cache hits, read data is returned by the cache.
  • On cache misses, read data is returned from main memory and not allocated (stored) in cache.
ATTRIBUTE VALUE NOTE
ARDOMAIN[1:0] ’b01 Inner Sharable
ARBAR[1:0] ‘b00 Normal access, respecting barriers
ARSNOOP[3:0] ‘b0000 ReadOnce
ARCACHE[3:0] ‘b1011 Write-back No-allocate
ARPROT[2:0] ‘b011 or ‘b010

Privileged access. Non-Secure access. Data access

(or could be ‘b010 for Unprivileged access)

ARLEN[7:0]

The burst length for:

WRAP burst type must be 1, 2, 4, 8 or 16 transfers.

INCR burst type is 1 to 256 transfers.

ARSIZE[2:0] The number of bytes in a transfer must be equal to the data bus width (128 bits)
ARBURST[1:0] ‘b01 or ‘b10 Must be INCR(‘b01) or WRAP(‘b10)
ARLOCK[1:0] ‘b00 Must be normal access
ARQOS Quality of Service. QoS identifier sent for each transaction. Implemented only in AXI4.

Writes

  • On cache hits, write data is stored in cache.
  • On cache misses, write data is stored to main memory.
ATTRIBUTE VALUE NOTE
AWDOMAIN[1:0] ’b01 Inner Sharable
AWBAR[1:0] ‘b00 Normal access, respecting barriers
AWSNOOP[2:0] ‘b000 WriteUnique (could be ‘b001 for WriteLineUnique)
AWCACHE[3:0] ‘b0111 Write-back No-allocate
AWPROT[2:0] ‘b011 or ‘b010

Privileged access. Non-Secure access. Data access

(or could be ‘b010 for Unprivileged access)

AWLEN[7:0]

The burst length for:

WRAP burst type must be 1, 2, 4, 8 or 16 transfers.

INCR burst type is 1 to 256 transfers.

AWSIZE[2:0] The number of bytes in a transfer must be equal to the data bus width (128 bits)
AWBURST[1:0] ‘b01 or ‘b10 Must be INCR(‘b01) or WRAP(‘b10)
AWLOCK[1:0] ‘b00 Must be normal access
AWQOS Quality of Service. QoS identifier sent for each transaction. Implemented only in AXI4.