Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.2.1.3. Stratix 10 MPU Address Space

The MPU address space is 132 GB, and applies to addresses generated by the MPU. MPU private registers (SCU and L2) and the GIC are visible only to the MPU. The MPU address map covers the entire HPS address map.

The MPU address space contains the following regions:

  • The boot region, starting at 0x_FFE0_0000 in RAM
  • The FPGA slaves window region, including the HPS-to-FPGA and lightweight HPS-to-FPGA regions
  • The peripheral region

The FPGA-to-HPS bridge sees the same address space as the MPU, except for private registers (SCU and L2) and the GIC, which are visible only to the MPU.

HPS-to-FPGA Slaves Region

The HPS-to-FPGA slaves region provides access to slaves in the FPGA fabric through the HPS-to-FPGA bridge.

Lightweight HPS-to-FPGA Slaves Region

The lightweight FPGA slaves provide access to slaves in the FPGA fabric through the lightweight HPS-to-FPGA bridge.

Peripherals Region

The peripheral region addresses 144 MB at the top of the first 4 GB address space. The peripheral region includes all slaves connected to the L3 Interconnect, L4 buses, and MPU registers (SCU and L2). The on-chip RAM is mapped into the peripheral region.

This region provides access to internally-decoded MPU registers (SCU and L2).

Generic Interrupt Controller Region

The GIC region provides access to the GIC control and status registers.

SCU and L2 Registers Region

The SCU and L2 registers region provides access to internally-decoded MPU registers (SCU and L2).