Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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13.3.1.6. GPIO Interconnect Between the HPS and FPGA

Thirty-two general purpose inputs and thirty-two general purpose outputs are provided to the FPGA and are controlled through registers in the System Manager. No interrupts are generated through the input pins. All inputs are synchronized within the System Manager. Output signals should be synchronized in the fabric.
  • h2f_gp_in [31:0]—Provides a low-latency, low-performance, and simple way to read general-purpose signals driven from the fabric. If the FPGA is not in User Mode, the value of this field is undefined.
  • h2f_gp_out [31:0]—Provides a low-latency, low-performance, and simple way to drive general-purpose signals to the fabric. When read returns the current value being driven to the fabric.