Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

13.1. Features of the System Manager

Software accesses the CSRs in the system manager to control and monitor various functions in other HPS modules that require external control signals. The system manager connects to these modules to perform the following functions:

  • Sends pause signals to pause the watchdog timers when the processors in the MPU system complex are in debug mode
  • Selects the EMAC system interconnect master access options and other EMAC clock and interface options.
  • Selects the SD/MMC controller clock options and system interconnect master access options.
  • Selects the NAND flash controller bootstrap options and system interconnect master access option.
  • Selects USB controller system interconnect master access option.
  • Provides control over the DMA security settings when the HPS exits from reset.
  • Provides the capability to enable or disable an interface to the FPGA.
  • Provides combined ECC status and interrupts from other HPS modules with ECC-protected RAM.
  • Routes parity failure interrupts from the L1 caches to the Global Interrupt Controller.