Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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2.2.11. CoreSight* Debug and Trace

The CoreSight* Debug and Trace system offers the following features:
  • Real-time program flow instruction trace through a separate Embedded Trace Macrocell (ETM) for each processor
  • Host debugger JTAG interface
  • Connections for cross-trigger and STM-to-FPGA interfaces, which enable soft IP cores to generate of triggers and system trace messages
  • Custom message injection through STM into trace stream for delivery to host debugger
  • Capability to route trace data to any slave accessible to the ETR master, which is connected to the L3 interconnect