Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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25.5. CoreSight Debug and Trace Programming Model

This section describes programming model details specific to Intel® 's implementation of the ARM® CoreSight technology.

The debug components can be configured to cause triggers when certain events occur. For example, soft logic in the FPGA fabric can signal an event which triggers an STM message injection into the trace stream.

For more information about the programming interface of each CoreSight component, refer to the ARM® Infocenter website.