Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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17.6.4.6. Frequency Range of Reference Timing Clock

The timestamp information is transferred across asynchronous clock domains, from the EMAC clock domain to the FPGA clock domain. Therefore, a minimum delay is required between two consecutive timestamp captures. This delay is four PHY interface clock cycles and three PTP clock cycles. If the delay between two timestamp captures is less than this amount, the MAC does not take a timestamp snapshot for the second frame.

The maximum PTP clock frequency is limited by the maximum resolution of the reference time (20 ns resulting in 50 MHz) and the timing constraints achievable for logic operating on the PTP clock. In addition, the resolution, or granularity, of the reference time source determines the accuracy of the synchronization. Therefore, a higher PTP clock frequency gives better system performance.

The minimum PTP clock frequency depends on the time required between two consecutive SFD bytes. Because the PHY interface clock frequency is fixed by the IEEE 1588 specification, the minimum PTP clock frequency required for proper operation depends on the operating mode and operating speed of the MAC.

Table 183.  Minimum PTP Clock Frequency Example

Mode

Minimum Gap Between Two SFDs

Minimum PTP Frequency

100‑Mbps full-duplex operation

168 MII clocks

(128 clocks for a 64-byte frame + 24 clocks of min IFG + 16 clocks of preamble)

(3 * PTP) + (4 * MII) <= 168 * MII, that is, ~0.5 MHz (168 – 4) * 40 ns ÷ 3 = 2180 ns period

1000-Mbps half duplex operation

24 GMII clocks

(4 for a jam pattern sent just after SFD because of collision + 12 IFG + 8 preamble)

(3 * PTP) + 4 * GMII <= 24 * GMII, that is, 18.75 MHz