Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.1.4.1. Features of the Stratix 10 HPS SDRAM L3 Interconnect

The SDRAM L3 interconnect supports the following features:
  • Connectivity to the SDRAM hard memory controller supporting:
    • DDR4-SDRAM
    • DDR3-SDRAM
  • Integrated SDRAM scheduler, functioning as a multi-port front end (MPFE)
  • Configurable external SDRAM interface data widths
    • 16-bit, with or without 8-bit error-correcting code (ECC)
    • 32-bit, with or without 8-bit ECC
    • 64-bit, with or without 8-bit ECC
  • High-performance ports
    • CCU port supporting coherent accesses for MPU L2 Cache master, HPS peripheral DMA masters, and FPGA masters through the FPGA-to-HPS Bridge
    • Three 32-, 64-, or 128-bit FPGA ports
    • Per-port firewall security support
  • 8-bit Single Error Correction, Double Error Detection (SECDED) ECC
Note: At system startup, the configuration bitstream can direct the SDM to configure the SDRAM I/O pins separately from the FPGA fabric, allowing the SoC HPS to boot before any soft logic is configured in the FPGA. This booting method is called HPS Boot First or Early I/O Configuration.