Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.9.4. SDRAM L3 Interconnect Resets

The reset signal l3_rst_n resets the system interconnect and the SDRAM L3 interconnect, but not the hard memory controller.

When you instantiate the HPS component, Platform Designer automatically connects the hard memory controller's reset signal to the SDRAM L3 interconnect.

Soft logic in the FPGA must support the global_reset_n signal correctly. Refer to Instantiating the HPS Component for information about global_reset_n.

You can optionally protect SDRAM contents during a warm reset. With the memory in DDR ×64 mode, the reset manager can issue a handshake request for the MPFE to stop accepting new read and write requests. After all pending transactions have completed, the MPFE acknowledges the handshake, and the reset manager initiates the warm reset.

With the memory in DDR ×32 or ×16 mode, the reset manager does not receive the acknowledge signal from the MPFE. In these cases, software must enable the handshake for the MPFE to stop accepting all transactions and issue a warm reset request. After the timeout, the reset manager initiates the warm reset.

To optionally preserve the contents of the SDRAM on reset, refer to "Reset Handshaking" in the "Reset Manager" chapter of the Stratix 10 Hard Processor System Technical Reference Manual.

Figure 27. Recommended SDRAM Reset Connections
Note: The input reference clock (pll_ref_clk) must be stable and free-running at device power-up for a successful configuration.
Note: It is important to connect the reset user logic directly to both the HPS and the hard memory controller. If the hard memory controller is reset while the HPS is still running, the HPS is unable to access any external SDRAM memory.