Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.1.4.2. SDRAM L3 Interconnect Block Diagram and System Integration

The SDRAM L3 interconnect consists of two main blocks: SDRAM adapter and SDRAM scheduler.

The SDRAM adapter is responsible for bridging the SDRAM scheduler to the hard memory controller (in the FPGA portion of the device). The adapter is also responsible for ECC generation and checking.

The ECC register interface provides control to perform memory and ECC logic diagnostics.

The SDRAM scheduler is a multi-port front end (MPFE) responsible for arbitrating collisions and optimizing performance in traffic to the SDRAM controller in the FPGA portion of the device.

The SDRAM L3 interconnect exposes three ARM Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI™) ports to the FPGA fabric, allowing soft logic masters to access the SDRAM controller through the same scheduler unit as the MPU system complex and other masters within the HPS. The MPU has access to the SDRAM adapter's control interface to the hard memory controller.

Figure 20. SDRAM L3 Interconnect Block Diagram

The SDRAM L3 interconnect has a dedicated connection to the hard memory controller in the FPGA portion of the device. This connection allows the hard memory controller to become operational before the rest of the FPGA has been configured.