Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

13.2. System Manager Block Diagram

The system manager connects to the level 4 (L4) bus through a slave interface. The CSRs connect to signals in the FPGA and other HPS modules.

Figure 44. System Manager Block Diagram

The system manager consists of the following:

  • CSRs—Provide memory-mapped access to control signals and status for the following HPS modules:
    • EMACs
    • Debug core
    • SD/MMC controller
    • NAND controller
    • USB controllers
    • DMA controller
    • System interconnect
    • GPIO interconnect between HPS and FPGA
    • ECC memory interfaces for the following peripherals:
      • USB controllers
      • SD/MMC controller
      • Ethernet MACs
      • DMA controller
      • NAND flash controller
      • On-chip RAM
  • Watchdog debug pause—accepts the debug mode status from the MPU system complex and pauses the L4 watchdog timers.
  • Reset Manager— system manager receives the reset signals from reset manager.