Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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4.2. Block Diagram

The CCU's coherency interconnect routes master agent transactions to the cache coherency components within the interconnect and ultimately, to the slave agents.

The CCU manages one-way coherency with the Cortex® -A53 MPCore™ . The CCU allows the master agents (masters connected to the CCU) to see the coherent memory of the Cortex® -A53 MPCore™ processor cores but does not allow the processor cores to be coherent with any caches external to the Cortex® -A53 MPCore™ processor.

Figure 7. CCU Block Diagram

The CCU Block Diagram shows the master agents of the CCU, the CCU components and the slaves that connect to it. The following master agent ports interface to the CCU:

  • The Cortex® -A53 MPCore™ port:
    • Connects the Cortex® -A53 MPCore™ subsystem to the CCU
    • Supports memory read and write requests, as well as I/O memory-mapped read and write requests
    • Includes read and write channels and their corresponding response channels
    • Supports channels for snoop requests, snoop responses and signals used as part of the coherency protocol to indicate response arrival.
  • The FPGA-to-HPS ACE-lite port connects the FPGA-to-HPS bridge to the CCU and supports I/O coherent requests to the CCU.
  • The peripheral master port supports I/O coherent and non-coherent requests to the CCU from masters connected to the level 3 (L3) interconnect.
  • The TCU port provides a page table walk interface to transfer I/O coherent requests to the CCU. This interface includes a DVM interface to send translation look-aside buffer (TLB) control information between the Cortex® -A53 MPCore™ and the system MMU.
The following slave bus ports interface to the CCU:
  • The external SDRAM port sends read and write transactions from the CCU to external memory through the L3 SDRAM interconnect.
  • The SDRAM register port is a dedicated interface to the L3 SDRAM scheduler, L3 SDRAM adapter , and hard memory controller registers.
  • The RAM port is a dedicated interface to the on-chip RAM.
  • The GIC port is a dedicated interface to the general interrupt controller (GIC).
  • The peripheral slave I/O port sends memory-mapped read and write requests to slave peripherals connected to the L3 interconnect.

The coherency bridge accepts requests from the ACE, ACE-lite + DVM and ACE-lite buses of the master agent ports. The coherency bridge sends these requests to the cache coherency controller.

The CCU directory tracks the state of the 1 MB L1 and L2 cache in the ARM® Cortex® -A53 MPCore™ .

The bridges control address range and QoS, and track the transmitting logic and FIFO status. You can control and view these features through registers in the CCU.

Routers within the CCU coherency interconnect send transactions to the appropriate coherency components within the CCU or to the appropriate slave port bridge where they are de-packetized and converted to the appropriate slave agent bus protocol.

Cacheable accesses from the Cortex® -A53 MPCore™ processor route directly to the CCU where the coherency directory is updated. The CCU forwards non-cacheable accesses directly to the slave .

Master agents with ACE-lite and ACE-lite + DVM bus interfaces send transactions to the I/O coherency bridge (IOCB) . The IOCB sends coherent requests to the cache coherency controller (CCC) where a directory lookup determines if the address resides within a cache line of the MPU L2 cache.

The distributed virtual memory (DVM) controller supports the AMBA* ACE DVM protocol. The DVM controller broadcasts and synchronizes control packets for TLB invalidations, cache invalidations and similar requests.