Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

11.3.3. Hardware-Managed and Software-Managed Clocks

When changing values on clocks, the terms hardware-managed and software-managed define how clock transitions are implemented. When changing a software-managed clock, software is responsible for gating off the clock, waiting for a PLL lock if required, and gating the clock back on. Clocks that are hardware-managed are automatically transitioned by the hardware to ensure glitch-free operation.

The hardware-managed clocks are:

  • mpu_periph_clk
  • mpu_l2_ram_clk
  • mpu_clk
  • l3_main_free_clk
  • l4_sys_free_clk
  • l4_sys_free_div4_clk
  • l4_main_clk
  • l4_mp_clk
  • l4_sp_clk
  • cs_at_clk
  • cs_pdbg_clk
  • cs_trace_clk
All other clocks in the HPS are software-managed clocks.
Note: During boot mode, all clocks are bypassed including both hardware-managed and software-managed clocks. Individual software bypass controls are available for each set of clocks.