Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.5.13.4. GIC Interrupt Map for the SoC HPS

Note: To ensure that you are using the correct GIC interrupt number, your code should refer to the symbolic interrupt name, as shown in the Interrupt Name column. Symbolic interrupt names are defined in a header file distributed with the source installation for your operating system.
Table 35.  GIC Interrupt Map

GIC Interrupt Number

Source Block

Interrupt Name

Description

32

Secure Device Manager (SDM)

SDM_IRQ0 (mailbox_intr)

SDM Mailbox Interrupt

35

Secure Device Manager (SDM)

SDM_IRQ3 (sdm_qspi_intr)

 SDM Quad SPI Interrupt

37

Secure Device Manager (SDM)

SDM_IRQ5 (sdm_sdmmc_irq)

 SDM SD/MMC Interrupt

47

System Manager

SERR_Global  Global System Error Interrupt

48

CCU

interrupt_ccu  CCU Combined Interrupt

49

FPGA

f2h_irq_p0[0] F2H FPGA Interrupt[0]

50

FPGA

f2h_irq_p0[1] F2H FPGA Interrupt[1]

51

FPGA

f2h_irq_p0[2] F2H FPGA Interrupt[2]

52

FPGA

f2h_irq_p0[3] F2H FPGA Interrupt[3]

53

FPGA

f2h_irq_p0[4] F2H FPGA Interrupt[4]

54

FPGA

f2h_irq_p0[5] F2H FPGA Interrupt[5]

55

FPGA

f2h_irq_p0[6] F2H FPGA Interrupt[6]

56

FPGA

f2h_irq_p0[7] F2H FPGA Interrupt[7

57

FPGA

f2h_irq_p0[8] F2H FPGA Interrupt[8]

58

FPGA

f2h_irq_p0[9] F2H FPGA Interrupt[9]

59

FPGA

f2h_irq_p0[10] F2H FPGA Interrupt[10]

60

FPGA

f2h_irq_p0[11] F2H FPGA Interrupt[11]

61

FPGA

f2h_irq_p0[12] F2H FPGA Interrupt[12]

62

FPGA

f2h_irq_p0[13] F2H FPGA Interrupt[13]

63

FPGA

f2h_irq_p0[14] F2H FPGA Interrupt[14]

64

FPGA

f2h_irq_p0[15] F2H FPGA Interrupt[15]

65

FPGA

f2h_irq_p0[16]  F2H FPGA Interrupt[16]

66

FPGA

f2h_irq_p0[17] F2H FPGA Interrupt[17]

67

FPGA

f2h_irq_p0[18]  F2H FPGA Interrupt[18]

68

FPGA

f2h_irq_p0[19] F2H FPGA Interrupt[19]

69

FPGA

f2h_irq_p0[20]  F2H FPGA Interrupt[20]

70

FPGA

f2h_irq_p0[21]  F2H FPGA Interrupt[21]

71

FPGA

f2h_irq_p0[22]  F2H FPGA Interrupt[22]

72

FPGA

f2h_irq_p0[23]  F2H FPGA Interrupt[23]

73

FPGA

f2h_irq_p0[24]  F2H FPGA Interrupt[24]

74

FPGA

f2h_irq_p0[25] F2H FPGA Interrupt[25]

75

FPGA

f2h_irq_p0[26] F2H FPGA Interrupt[26]

76

FPGA

f2h_irq_p0[27] F2H FPGA Interrupt[27]

77

FPGA

f2h_irq_p0[28] F2H FPGA Interrupt[28]

78

FPGA

f2h_irq_p0[29] F2H FPGA Interrupt[29]

79

FPGA

f2h_irq_p0[30] F2H FPGA Interrupt[30]

80

FPGA

f2h_irq_p0[31] F2H FPGA Interrupt[31]

81

FPGA

f2h_irq_p1[0] F2H FPGA Interrupt[32]

82

FPGA

f2h_irq_p1[1] F2H FPGA Interrupt[33]

83

FPGA

f2h_irq_p1[2] F2H FPGA Interrupt[34]

84

FPGA

f2h_irq_p1[3] F2H FPGA Interrupt[35]

85

FPGA

f2h_irq_p1[4] F2H FPGA Interrupt[36]

86

FPGA

f2h_irq_p1[5] F2H FPGA Interrupt[37]

87

FPGA

f2h_irq_p1[6] F2H FPGA Interrupt[38]

88

FPGA

f2h_irq_p1[7] F2H FPGA Interrupt[39]

89

FPGA

f2h_irq_p1[8] F2H FPGA Interrupt[40]

90

FPGA

f2h_irq_p1[9] F2H FPGA Interrupt[41]

91

FPGA

f2h_irq_p1[10] F2H FPGA Interrupt[42]

92

FPGA

f2h_irq_p1[11] F2H FPGA Interrupt[43]

93

FPGA

f2h_irq_p1[12] F2H FPGA Interrupt[44]

94

FPGA

f2h_irq_p1[13] F2H FPGA Interrupt[45]

95

FPGA

f2h_irq_p1[14] F2H FPGA Interrupt[46]

96

FPGA

f2h_irq_p1[15] F2H FPGA Interrupt[47]

97

FPGA

f2h_irq_p1[15] F2H FPGA Interrupt[48]

98

FPGA

f2h_irq_p1[17] F2H FPGA Interrupt[49]

99

FPGA

f2h_irq_p1[18] F2H FPGA Interrupt[50]

100

FPGA

f2h_irq_p1[19] F2H FPGA Interrupt[51]

101

FPGA

f2h_irq_p1[20] F2H FPGA Interrupt[52]

102

FPGA

f2h_irq_p1[21] F2H FPGA Interrupt[53]

103

FPGA

f2h_irq_p1[22] F2H FPGA Interrupt[54]

104

FPGA

f2h_irq_p1[23] F2H FPGA Interrupt[55]

105

FPGA

f2h_irq_p1[24] F2H FPGA Interrupt[56]

106

FPGA

f2h_irq_p1[25] F2H FPGA Interrupt[57]

107

FPGA

f2h_irq_p1[26] F2H FPGA Interrupt[58]

108

FPGA

f2h_irq_p1[27] F2H FPGA Interrupt[59]

109

FPGA

f2h_irq_p1[28] F2H FPGA Interrupt[60]

110

FPGA

f2h_irq_p1[29] F2H FPGA Interrupt[61]

111

FPGA

f2h_irq_p1[30] F2H FPGA Interrupt[62]

112

FPGA

f2h_irq_p1[31] F2H FPGA Interrupt[63]

113

DMA

dma_IRQ0 DMA Interrupt 0

114

DMA

dma_IRQ1 DMA Interrupt 1

115

DMA

dma_IRQ2 DMA Interrupt 2

116

DMA

dma_IRQ3 DMA Interrupt 3

117

DMA

dma_IRQ4 DMA Interrupt 4

118

DMA

dma_IRQ5 DMA Interrupt 5

119

DMA

dma_IRQ6 DMA Interrupt 6

120

DMA

dma_IRQ7 DMA Interrupt 7

121

DMA

dma_irq_abort DMA Abort Interrupt

122

EMAC0

emac0_IRQ EMAC0 Interrupt

123

EMAC1

emac1_IRQ EMAC1 Interrupt

124

EMAC2

emac2_IRQ EMAC2 Interrupt

125

USB0

usb0_IRQ USB0 Interrupt

126

USB1

usb1_IRQ USB1 Interrupt

127

MPFE

HMC_error DDR4 Protocol Error Interrupt

128

SDMMC

sdmmc_IRQ SD/MMC Interrupt

129

NAND

nand_IRQ NAND Interrupt

130

Reserved

Reserved

 -

131

SPI0 master

spim0_IRQ SPI0 Master Interrupt

132

SPI1 master

spim1_IRQ SPI1 Master Interrupt

133

SPI0 slave

spis0_IRQ SPI0 Slave Interrupt

134

SPI1 slave

spis1_IRQ SPI1 Slave Interrupt

135

I2C0

i2c0_IRQ I2C0 Interrupt

136

I2C1

i2c1_IRQ I2C1 Interrupt

137

I2C2

i2c2_IRQ I2C2 Interrupt (I2C2 can be used with EMAC0)

138

I2C3

i2c3_IRQ I2C3 Interrupt (I2C3 can be used with EMAC1)

139

I2C4

i2c4_IRQ I2C4 Interrupt (I2C4 can be used with EMAC2)

140

UART0

uart0_IRQ

UART0 Interrupt

141

UART1

uart1_IRQ UART1 Interrupt

142

GPIO0

gpio0_IRQ

GPIO 0 Interrupt

143

GPIO1

gpio1_IRQ

GPIO 1 Interrupt

144

Reserved

-

 -

145

Timer0

timer_l4sp_0_IRQ

Timer0 Interrupt

146

Timer1

timer_l4sp_1_IRQ

Timer1 Interrupt

147

Timer2

timer_osc1_0_IRQ

Timer 2 Interrupt

148

Timer3

timer_osc1_1_IRQ

Timer 3 Interrupt

149

Watchdog0

wdog0_IRQ Watchdog0 Interrupt

150

Watchdog1

wdog1_IRQ Watchdog1 Interrupt

151

Clock Manager

clkmgr_IRQ Clock Manager Interrupt

152

SDRAM MPFE

seq2core Calibration Interrupt

153

CoreSight CPU0 CTI

CTIIRQ[0] Cortex-A53 MPCore™ Processor CPU 0 Cross Trigger Interface Interrupt

154

CoreSight CPU1 CTI

CTIIRQ[1] Cortex-A53 MPCore™ Processor CPU 1 Cross Trigger Interface Interrupt

155

CoreSight CPU2 CTI

CTIIRQ[2] Cortex-A53 MPCore™ Processor CPU 2 Cross Trigger Interface Interrupt

156

CoreSight CPU3 CTI

CTIIRQ[3] Cortex-A53 MPCore™ Processor CPU 3 Cross Trigger Interface Interrupt

157

Watchdog2

wdog2_IRQ Watchdog 2 Interrupt

158

Watchdog3

wdog3_IRQ Watchdog 3 Interrupt

159

Cortex® -A53 nEXTERRIRQ Cortex-A53 MPCore™ External Error Interrupt

160

System MMU

gbl_flt_irpt_s Global Secure Fault Interrupt

161

System MMU

gbl_flt_irpt_ns Global Non-secure Fault Interrupt

162

System MMU perf_irpt_FPGA_TBU FPGA TBU Performance Counter Interrupt

163

System MMU perf_irpt_DMA_TBU DMA TBU Performance Counter Interrupt

164

System MMU perf_irpt_EMAC_TBU EMAC TBU Performance Counter Interrupt

165

System MMU perf_irpt_IO_TBU Peripheral I/O Master TBU Performance Counter Interrupt

167

Reserved

Reserved

 -

168

System MMU comb_irpt_ns

System MMU Combined Non-secure Interrupt

169

System MMU comb_irpt_s System MMU Combined Secure Interrupt

170

System MMU cxt_irpt_0 System MMU Non-secure Context Interrupt 0

171

System MMU cxt_irpt_1 System MMU Non-secure Context 1 Interrupt

172

System MMU cxt_irpt_2 System MMU Non-secure Context 2 Interrupt

173

System MMU cxt_irpt_3 System MMU Non-secure Context 3 Interrupt

174

System MMU cxt_irpt_4 System MMU Non-secure Context 4 Interrupt

175

System MMU cxt_irpt_5 System MMU Non-secure Context 5 Interrupt

176

System MMU cxt_irpt_6 System MMU Non-secure Context 6 Interrupt

177

System MMU cxt_irpt_7 System MMU Non-secure Context 7 Interrupt

178

System MMU cxt_irpt_8 System MMU Non-secure Context 8 Interrupt

179

System MMU cxt_irpt_9 System MMU Non-secure Context 9 Interrupt

180

System MMU cxt_irpt_10 System MMU Non-secure Context 10 Interrupt

181

System MMU cxt_irpt_11 System MMU Non-secure Context 11 Interrupt

182

System MMU cxt_irpt_12 System MMU Non-secure Context 12 Interrupt

183

System MMU cxt_irpt_13 System MMU Non-secure Context 13 Interrupt

184

System MMU cxt_irpt_14 System MMU Non-secure Context 14 Interrupt

185

System MMU cxt_irpt_15 System MMU Non-secure Context 15 Interrupt

186

System MMU cxt_irpt_16 System MMU Non-secure Context 16 Interrupt

187

System MMU cxt_irpt_17 System MMU Non-secure Context 17 Interrupt

188

System MMU cxt_irpt_18 System MMU Non-secure Context 18 Interrupt

189

System MMU cxt_irpt_19 System MMU Non-secure Context 19 Interrupt

190

System MMU cxt_irpt_20 System MMU Non-secure Context 20 Interrupt

191

System MMU cxt_irpt_21 System MMU Non-secure Context 21 Interrupt

192

System MMU cxt_irpt_22 System MMU Non-secure Context 22 Interrupt

193

System MMU cxt_irpt_23 System MMU Non-secure Context 23 Interrupt

194

System MMU cxt_irpt_24 System MMU Non-secure Context 24 Interrupt

195

System MMU cxt_irpt_25 System MMU Non-secure Context 25 Interrupt

196

System MMU cxt_irpt_26 System MMU Non-secure Context 26 Interrupt

197

System MMU cxt_irpt_27 System MMU Non-secure Context 27 Interrupt

198

System MMU cxt_irpt_28 System MMU Non-secure Context 28 Interrupt

199

System MMU cxt_irpt_29 System MMU Non-secure Context 29 Interrupt

200

System MMU cxt_irpt_30 System MMU Non-secure Context 30 Interrupt

201

System MMU cxt_irpt_31 System MMU Non-secure Context 31 Interrupt

202

Cortex® -A53 nPMUIRQ[0] Cortex® -A53 Processor CPU 0 Performance Monitor Interrupt

203

Cortex® -A53 nPMUIRQ[1] Cortex® -A53 Processor CPU 1 Performance Monitor Interrupt

204

Cortex® -A53 nPMUIRQ[2] Cortex® -A53 Processor CPU 2 Performance Monitor Interrupt

205

Cortex® -A53 nPMUIRQ[3] Cortex® -A53 Processor CPU 3 Performance Monitor Interrupt