Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.5.4.3. Initializing the Instruction and Data Caches

Follow these steps for each execution level (EL) that you use in the system.
  1. Enable data coherency by setting the SMPEN bit in the CPU Extended Control Register (CPUTECTR).
  2. Invalidate all instruction cache entries by setting the I bit in the System Control Registers (SCTLR_ELx), where x indicates the execution level.
  3. Invalidate all entries in the data cache.
  4. Invalidate the TLB contents.
  5. Configure the CPU MMUs (the data cache is not active unless the MMUs are also active).
    1. Configure the page tables.
    2. Configure the Translation Table Base Registers (TTBR) for each execution level.
  6. Set the M bit in the SCTRL_ELx register to enable the MMU.
  7. Set the C bit in the SCTRL_ELx register to enable the data cache.