Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

19.5.2. Master Microwire Serial Transfers

Figure 105. Microwire Serial

To complete a Microwire serial transfer from the SPI master, follow these steps:

  1. If the SPI master is enabled, disable it by writing 0 to SPIENR.
  2. Set up the SPI control registers for the transfer. You can set these registers in any order.
    • Write CTRLR0 to set transfer parameters. If the transfer is sequential and the SPI master receives data, write CTRLR1 with the number of frames in the transfer minus 1. For example, if you want to receive four data frames, write 3 to this register.
    • Write BAUDR to set the baud rate for the transfer.
    • Write TXFTLR and RXFTLR to set FIFO buffer threshold levels.
    • Write the IMR register to set up interrupt masks.

    You can write the SER register to enable the target slave for selection. If a slave is enabled here, the transfer begins as soon as one valid data entry is present in the transmit FIFO buffer. If no slaves are enabled prior to writing to the DR register, the transfer does not begin until a slave is enabled.

  3. Enable the SPI master by writing 1 to the SPIENR register.
  4. If the SPI master transmits data, write the control and data words into the transmit FIFO buffer (write DR). If the SPI master receives data, write the control word or words into the transmit FIFO buffer. If no slaves were enabled in the SER register at this point, enable now to begin the transfer.
  5. Poll the BUSY status to wait for the transfer to complete. If a transmit FIFO empty interrupt request is made, write the transmit FIFO buffer (write DR). If a receive FIFO full interrupt request is made, read the receive FIFO buffer (read DR).
  6. The shift control logic stops the transfer when the transmit FIFO buffer is empty. If the transfer mode is sequential and the SPI master receives data, the shift control logic stops the transfer when the specified number of data frames is received. When the transfer is done, the BUSY status is reset to 0.
  7. If the SPI master receives data, read the receive FIFO buffer until it is empty.
  8. Disable the SPI master by writing 0 to SPIENR.