Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.1.1.1. System Interconnect High-Level View

This figure shows the system interconnect, including the main L3 interconnect and SDRAM L3 interconnect.
Figure 13. High-Level System Interconnect Block DiagramThis figure shows the high-level relationships among the system interconnect and other major SoC components. For variable-bandwidth interfaces, the maximum bandwidth is shown.