Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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16.4.3.1.8. Send CCSD Command

If the send_ccsd bit in the ctrl register is set to 1, the controller sends a CCSD pattern on the CMD line. The host can send the CCSD command while waiting for the CCS or after a CCS timeout happens.

After sending the CCSD pattern, the controller sets the cmd bit in the rintsts register and also generates an interrupt to the host if the Command Done interrupt is not masked.

Note: Within the CIU block, if the send_ccsd bit in the ctrl register is set to 1 on the same clock cycle as CCS is sampled, the CIU block does not send a CCSD pattern on the CMD line. In this case, the dto and cmd bits in the rintsts register are set to 1.
Note: Due to asynchronous boundaries, the CCS might have already happened and the send_ccsd bit is set to 1. In this case, the CCSD command does not go to the CE‑ATA card device and the send_ccsd bit is not set to 0. The host must reset the send_ccsd bit to 0 before the next command is issued.

If the send auto stop CCSD (send_auto_stop_ccsd) bit in the ctrl register is set to 1, the controller sends an internally generated STOP_TRANSMISSION command (CMD12) after sending the CCSD pattern. The controller sets the acd bit in the rintsts register.