Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.2.9.2.1. ECC

The SDRAM Adapter ECC can detect and correct single-bit errors and detect double-bit errors.
The ECC hardware merges the addresses with data and uses the result for error checking. This configuration detects if correct write data is written to an incorrect location in memory; and if correct data is read from an incorrect location in memory.
Note: The hardware detects data and address errors independently.

ECC Write Behavior

When data is written to SDRAM, the SDRAM controller generates an ECC based on the write data and the write address.

If the write transaction is a partial write (less than 64 bits wide), the SDRAM adapter implements it as a read-modify-write (RMW) sequence, as follows:

  1. Reads existing data from the specified address
  2. Combines the write data with the existing data
  3. Generates the ECC based on the combined data and the write address
  4. Writes the combined data back to the write address

ECC Read Behavior

When the SDRAM controller reads data from SDRAM, it checks the ECC to determine if the data or address is incorrect. It handles the following cases:

  • If the SDRAM controller finds a single-bit data error, it corrects in the data returned to the master.
    Note: Intel recommends that you enable the SDRAM adapter to write the corrected data back to memory, to avoid uncorrectable double-bit errors.
  • If the SDRAM controller finds a double-bit data error, the SDRAM L3 interconnect issues an interrupt. The ECC hardware cannot correct double-bit errors.
  • If the SDRAM controller finds an error in the address, indicating an address bit upset between the adapter and the hard memory controller, the SDRAM L3 interconnect hardware issues a bus error.