Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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20.5.1.1. Initial Configuration

To use the I2C controller as a slave, perform the following steps: †

  1. Disable the I2C controller by writing a 0 to bit 0 of the IC_ENABLE register. †
  2. Write to the IC_SAR register (bits 9:0) to set the slave address. This is the address to which the I2C controller responds. †
    Note: The reset value for the I2C controller slave address is 0x55. If you are using 0x55 as the slave address, you can safely skip this step.
  3. Write to the IC_CON register to specify which type of addressing is supported (7- or 10-bit by setting bit 3). Enable the I2C controller in slave-only mode by writing a 0 into bit 6 (IC_SLAVE_DISABLE) and a 0 to bit 0 (MASTER_MODE). †
    Note: Slaves and masters do not have to be programmed with the same type of addressing 7- or 10-bit address. For instance, a slave can be programmed with 7-bit addressing and a master with 10-bit addressing, and vice versa. †
  4. Enable the I2C controller by writing a 1 in bit 0 of the IC_ENABLE register. †
    Note: It is recommended that the I2C Slave be brought out of reset only when the I2C bus is IDLE. De-asserting the reset when a transfer is ongoing on the bus causes internal flip-flops used to synchronize SDA and SCL to toggle from a reset value of 1 to the actual value on the bus. In this scenario, if SDA toggling from 1 to 0 while SCL is 1, thereby causing a false START condition to be detected by the I2C Slave by configuring the I2C with IC_SLAVE_DISABLE = 1 and IC_MASTER_MODE = 1 so that the Slave interface is disabled after reset. It can then be enabled by programming IC_CON[0] = 0 and IC_CON[6] = 0 after the internal SDA and SCL have synchronized to the value on the bus; this takes approximately 6 ic_clk cycles after reset de-assertion.†