Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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12.3. Reset Handshaking

The reset manager participates in several reset handshaking protocols to ensure that the interfaces to other modules are precisely shut-down before the reset is applied.

  • Handshake with Clock Manager:
    • After assertion of a cold or warm reset, the reset manager requests clock manager to put clocks in boot mode.
  • Before the module reset signals are triggered by a warm reset, the reset manager performs handshakes with these modules to allow them to prepare for a warm reset. For example, debug AXI buses are made idle before asserting warm reset signal to non-debug logic. The handshake logic ensures the following conditions:
    • The embedded trace router (ETR) master has no pending master transactions to the L3 interconnect
    • The SDRAM Controller Subsystem stops accepting any new transactions and allows all outstanding transactions to drain
    • Warns the FPGA fabric of the forthcoming warm reset
  • Similarly, the handshake logic associated with ETR also occurs during the debug reset to ensure that the ETR master has no pending master transactions to the L3 interconnect before the debug reset is issued. This action ensures that when ETR undergoes a debug reset, the reset has no adverse effects on the system domain portion of the ETR.
Handshake Scenarios
  1. When the reset request is only for debug logic and not for system interconnect.
    • Reset manager asserts an idle request, indicating system interconnect to flush or complete all accesses, which is followed by a debug reset assertion.
  2. When the reset request is only for system interconnect and not for debug logic.
    • Reset manager asserts an idle request, indicating system interconnect to flush or complete all accesses, which is followed by a system interconnect reset assertion.
This handshaking applies to all debug logic and debug peripherals residing outside the warm reset domain.

When performing debug domain reset, the reset manager performs other debug related handshakes (ETR) before resetting the debug domains.